Multi-GPU Kernels, Intelligence per Watt, Heterogeneous Inference, and More | YC Paper Club

Y Combinator1h 16mJul 29, 2026
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AI Opinion

The episode most convincingly argues that specialized hardware, like TPUs, is essential for efficient AI, and that frameworks like Parallel Kittens offer a promising path toward simplifying complex GPU programming—both claims supported by concrete examples and performance comparisons. However, the assertion about training data centers orbiting the sun relies on speculative future developments rather than current realities, and the claim regarding Triton’s restrictiveness lacks detailed justification. Listeners should critically evaluate any predictions concerning long-term trends in software frameworks or hardware deployment strategies, and consider whether the presented economic impact metrics fully account for all relevant factors.

Avatars are AI rewrites of the same facts — style changes, not substance.

Summary

This discussion explores emerging trends and challenges in GPU programming and hardware design, particularly focusing on the shift towards specialized solutions for both training and inference AI models. A key theme is addressing memory bandwidth limitations through architectures like "System B" which offloads certain tasks to spatial reconfigurable machines. The conversation highlights speculative decoding using heterogeneous systems, the potential of game engines as efficient simulation environments, and the need for abstraction layers in GPU programming akin to Python's simplicity. Furthermore, it covers topics such as optimizing reinforcement learning simulations by leveraging GPUs, tackling the complexities of batch size one inference, and quantifying AI’s economic impact through metrics like “intelligence per watt.” The emergence of frameworks like Parallel Kittens (PK) demonstrates a path toward simplifying multi-GPU kernel development while maintaining high performance. Finally, the discussion touches on infrastructure considerations, including data center design, power management, and the rise of specialized hardware for inference workloads.

Avatars are AI rewrites of the same facts — style changes, not substance.

Key Points

00:26

Specialization in Chip Design for Training vs. Inference

The speaker observes a growing trend of specialization at the chip level, driven by increasing demand and the need for tailored hardware solutions. He highlights that training data centers require different specifications than inference data centers; training doesn't necessitate high bandwidth, whereas inference does. This shift is exemplified by Google’s TPU8 Zebra Fish and Sunfish, marking a move towards more specialized ASICs.

03:01

CPU Bottleneck in Reinforcement Learning Simulations

Brennan points out a significant bottleneck in reinforcement learning (RL) simulations: the environment.step function is often still executed on CPUs, hindering rollout speed and making classic RL challenging. This highlights an opportunity to leverage GPUs for this computationally intensive task, although it's currently framed as 'weird GPU usage'.

04:21

Batch Size One Inference Challenges

The speaker introduces the concept of batch size one inference and the challenges it presents. Prioritizing latency in applications like voice agents (e.g., phone calls) necessitates single-instance processing, which can be computationally expensive and resource-intensive, leading to delays if not optimized for specialized hardware.

04:47

Data Center Specialization and Location Flexibility

For training models, the primary metric is time per step, and location flexibility is key. Training data centers can be located far from users, even orbiting the sun, as long as efficient interconnects facilitate gradient communication. This contrasts with inference, which requires more localized processing for low latency.

15:53

Choosing the Right Transfer Mechanism is Crucial

The speaker emphasizes that selecting the appropriate transfer mechanism—whether it's TMA or the copy engine—is vital for optimal performance. For common multi-GPU operations like all-gather gem, TMA proves more efficient than relying solely on the copy engine. This choice significantly impacts data throughput and overall workload efficiency based on message size.

16:15

IntraSM vs InterSM Overlapping Trade-offs

The discussion introduces two primary strategies for scheduling inter-GPU communication with intra-GPU work: intraSM overlapping and interSM overlapping. IntraSM involves dedicating threads within a SM to either computation or communication (warp specialization), while interSM assigns entire SMs to communication, sacrificing some compute resources. Each approach presents trade-offs regarding performance and resource utilization.

19:13

Parallel Kittens Framework Simplifies Multi-GPU Programming

The Parallel Kittens (PK) framework builds upon previous work like Thunder Kittens, providing a set of CUDA programming primitives designed to simplify multi-GPU kernel development. PK abstracts away low-level complexities by offering data structures for each layer in the memory hierarchy (registers, shared memory, L2 cache, global memory) and communication primitives that automatically select efficient transfer mechanisms.

20:38

PK Achieves Performance Comparable to Hand-Optimized Kernels

The speaker highlights the impressive performance of Parallel Kittens (PK), noting that with just 50 to 100 lines of device code, it can match or surpass hand-optimized kernels often containing hundreds or even thousands of lines. This demonstrates PK's ability to significantly reduce development effort while maintaining high levels of efficiency.

30:18

Quantifying AI's Economic Impact

Stuart discussed the importance of quantifying the impact of increased 'intelligence per watt,' specifically mentioning potential effects on GDP and wages. He indicated that a forthcoming release would detail these metrics, suggesting a focus on translating computational advancements into tangible economic benefits. This highlights a shift towards measuring not just performance but also real-world utility.

30:34

Open Jarvis: On-Device AI

The team is developing 'Open Jarvis,' a project aimed at operationalizing insights and enabling personal AI coding stacks to run directly on devices like laptops and workstations. This initiative seeks to reduce reliance on cloud services such as OpenAI's LMS, offering users greater autonomy and potentially lower costs by shifting processing power locally.

33:06

The Spectrum of GPU Kernel Programming

Mark outlined a spectrum of GPU kernel programming languages, ranging from mathematical expressions to BTX/inline assembly. He categorized these options based on trade-offs between performance and productivity, noting that developers must choose the tools best suited for their priorities. This includes established libraries like PyTorch, Triton, CUDA, as well as newer approaches like ThunderCons, Cutless, and QDSL.

34:34

KernelBot: A Platform for Kernel Analysis

Mark introduced 'KernelBot,' a platform designed to analyze GPU kernel submissions. Users can submit kernels written in various libraries, allowing for data-driven insights into the popularity and usage patterns of different programming tools. This aims to provide valuable feedback on which approaches are most effective within the community.

45:10

AMDall's Law and Kernelms Bottlenecks

The speaker notes that kernelms exacerbate AMDall's law effects, meaning they tend to expose bottlenecks within a system. These bottlenecks can manifest as slow compilation times or any situation involving waiting, highlighting the need for optimization strategies. The discussion emphasizes the importance of addressing these inefficiencies to improve overall performance and reduce latency.

46:32

GP Mode as 'Pay-to-Win'

The speaker observes a trend where GP mode has effectively become 'pay-to-win' due to the extended test time scaling, often spanning days or weeks. This implies that those with greater resources (compute power and time) have an unfair advantage in testing and validation, creating a barrier for smaller teams or individuals.

47:24

Heterogeneous Infrastructure for Inference

Misha introduces Marlo, a startup focused on building workload-optimized heterogeneous infrastructure. The core premise is that inference isn't uniform; different phases (prefix cache lookup, prefill, KV cache creation, autoregressive decode) demand varying resources like compute, network bandwidth, storage, and memory. Therefore, co-designing systems with specialized hardware for each phase is crucial for efficiency.

50:01

Arithmetic Intensity and Roofline Model

Misha explains the concept of arithmetic intensity – the ratio of floating-point operations (flops) to data movement. He introduces the roofline model, originally developed for HPC, which helps determine whether a kernel is compute-bound or memory bandwidth-bound based on this ratio and machine characteristics. Understanding this relationship is key to optimizing performance by targeting bottlenecks.

01:00:04

Addressing Memory Bandwidth Limitations with System B

The discussion highlights that memory bandwidth often acts as a significant bottleneck in GPU performance. To overcome this, the speaker proposes introducing 'System B,' designed to efficiently handle latency-bound kernels and memory bandwidth limitations. This involves offloading specific tasks, such as MA kernels, to SRM (Spatial Reconfigurable Machine) machines which offer low latency due to their on-die architecture, extending the interactivity lifespan of the GPU.

01:01:37

Speculative Decoding with Heterogeneous Systems

The speaker discusses speculative decoding as an application for heterogeneous systems. In this process, a 'drafter' generates potential token sequences which are then verified in parallel by a 'verifier.' By running the drafter on System B (optimized for speed) and the verifier on System A, it is possible to achieve faster forward progress and improved overall latency compared to running both components on System A alone.

01:03:11

Heterogeneous Infrastructure Considerations

The speaker emphasizes that designing heterogeneous infrastructure is a full-stack problem with implications beyond just hardware. This includes data center considerations like power density and cooling, as well as networking challenges to avoid bottlenecks. Performance modeling through simulation is crucial for guiding design choices and ensuring efficient operation of the combined systems.

01:05:12

Game Engines as Efficient Learning Environments

The speaker introduces the concept of using game engines as learning environments, particularly for roboticists and self-driving car researchers. However, traditional game engine implementations are inefficient for high-throughput training workloads due to resource contention between parallel copies. The solution lies in 'batch simulators,' a single game engine simulating multiple instances concurrently.

01:15:22

Abstraction Layer Needed for GPU Programming

Brandon suggests that there's a significant opportunity to create abstraction layers in GPU programming. These abstractions should provide good default performance while utilizing raw GPU horsepower, ultimately simplifying the process of GPU programming. He draws an analogy to Python, envisioning something similar for GPUs – a scripting language that abstracts away much of the complexity.

Chapters

7 chapters · 21 key moments
KEYkey momentNot checkable herePartially supportedUnverifiedWell-supported

Claims & Fact Check

The TPU8 Zebra Fish and Sunfish represent the first instance of chip-level specialization.

Not checkable here

Batch size one inference is expensive and resource-intensive.

±Partially supported

Training data centers can be located far from users, even orbiting the sun.

Not checkable here

TMA is able to saturate the NV link with roughly 15 SMS.

?Unverified

Stripping out intermediate buffers in nickel can speed up all reduce by up to 80%.

?Unverified

PK is able to surpass or match hand optimized kernels that are often hundreds to thousands lines of code.

±Partially supported

Quantifying AI's impact on GDP and wages will be released soon.

Not checkable here

PyTorch’s front-end API will stand the test of time.

Not checkable here

Triton programming model is restrictive and not letting people write state-of-the-art kernels.

Not checkable here

Kernelms exacerbate AMDall's law effects.

?Unverified

GP mode has become pay-to-win due to long test time scaling.

Not checkable here

Inference is a very heterogeneous workload.

?Unverified

Introducing 'System B' can extend GPU interactivity by offloading memory bandwidth-bound kernels.

±Partially supported

Heterogeneous systems introduce data center challenges related to power density and cooling.

Well-supported

Game engines are inefficient for high-throughput training workloads when run in parallel.

±Partially supported

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